The present invention relates to digital controllers and more particularly to preventing degradation of dynamic performance of digital controllers due to phase lagging.
Most of the digital controllers of power converters developed up to now are based on a conventional architecture in which Analog-to-Digital Converters (ADCs) digitize the ADCs' state variables. In these digital controllers, a digital control algorithm determines a duty-cycle, which is used to drive a digital Pulse Width Modulator (PWM) for providing a Proportional Integration and Derivation (PID) compensation signal. Such PID compensation signal introduces undesired phase lagging due to the sampling effect and control delays, which include latency delay and clock based signal processing. The phase lagging leads to degraded dynamic performance of the digital controllers.
One of major challenges in digital control are quantization effects. The DPWM and ADC are two major quantizers in digital-controlled power converters. The duty cycle exported by the DPWM can only have discrete values, and the resolution of the discrete duty cycle ultimately determines the resolution of the output voltage. If there is no desired output voltage value inside the zero-error bin of the ADC, limit cycle oscillations will happen. A high DPWM resolution can greatly reduce the limit cycle oscillations. Therefore, a high frequency and high-resolution design of the DPWM becomes a major challenge in the implementation of the digitally controlled power converters having reasonable die size.
Further, light load efficiency is becoming a more and more important factor in choosing PWM controllers. Currently, to achieve a high-frequency and high resolution DPWM, high clock frequencies have to be used, making the related power consumption intolerable as compared to analog counterparts to the PWM controllers.